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In surface mount
technology (SMT), the chip carriers are mounted on printed circuit boards
(PCBs) by use of solder joints that provide both electrical and mechanical
connections. Near-eutectic Sn-Pb solder alloy (63%Sn-37%Pb) is the most
commonly used interconnect material.
During their service lives, electronic
assemblies encounter various environments that affect their structural
integrity, even cause their malfunctioning. Since the solder undergoes
high creep strains at even moderate temperatures, the effects of service
conditions on solder joints are vital for the functioning of the assemblies.
Among these harsh environments, temperature variations are known to be
the most harmful.
Fatigue failures in the solder joints
may occur even though the cyclic thermal stresses and strains generated
may be well below the yield limits. For this reason, the failures are immature
and unexpected.
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Research at the CAD/CAM Laboratory involves
the fatigue life prediction of solder joints with the use of Finite Element
Analysis (FEA). Two and three dimensional finite element models are constructed
and analyzed under the thermal loads. The stress and strain (which includes
elastic, plastic and creep strains) response is then used to calculate
the total strain energy absorbed by the joint within a cycle. This value
is used to predict the fatigue life of the joint using the fatigue life
prediction criterion developed in the CAD/CAM Lab.
Below is the finite element mesh constructed
to represent 1/8th of a chip carrier. Symmetry surfaces are assumed at
the chip center-line and at the diagonal lines, which enabled the use of
a 1/8th model instead of a complete model.
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