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The interrupt priority is an issue only when two interrupts are waiting to be serviced. For example if during an IDIV instruction (which takes 12 clock cycles), two interrupts occur, the interrupt with the highest priority will be serviced first. The 68HC12 has no mechanism to allow only interrupts with a higher priority to interrupt another interrupt in progress. If the I flag is cleared, any interrupt that occurs will interrupt any other interrupt service routine in progress. However, a selective mechanism is available on many other processors to keep lower priority inputs from interupting a currently executing ISR.