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Input Capture Specifics
Pins: The input capture hardware shares pins 7 through 9 and 12 through 16 with Port T. (IOCn shares PTn.)
Flags: C7F through C0F of TFLG1
- Set by active transitions on corresponding pins.
- Cleared by writing a 1 to the corresponding bit.
Interrupt Enable Bits: C7I through C0I of TMSK1
- Interrupt is enabled when corresponding bit is set (one), disabled otherwise.
But what exactly is an event?
Input capture involves quite a few entities. For each of the eight channels, we have a designator bit IOSn in the TIOS register to specify whether channel n is to be used for input capture or for output compare, a register TCn to hold the counter value corresponding to the occurrence of an event, a pin IOCn on which the signal constituting the event occurs, a flag CnF in the TFLG1 register that is set when the event occurs, an interrupt enable bit CnI in the TMSK1 register that allows an interrupt service routine to be called when the event occurs, and finally two edge selection bits EDGnB and EDGnA in either the TCTL3 or TCTL4 register (depending on the value of n).
So far we've covered all of these except the edge selection bits. We'll address the function and use of the edge selection bits in the next two slides.