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Input Capture Events: Edge select
The Input Capture Edge Control Bits occur in pairs, e.g. Bits 7 and 6 of TCTL3 comprise EDG7B and EDG7A, respectively.
For channel n, the edge is configured as follows:
- EDGnB EDGnA Configuration
- 0 0 capture disabled
- 0 1 event occurs on rising edge
- 1 0 event occurs on falling edge
- 1 1 event occurs on either edge
Bits of the TCTL3 and TCTL4 registers are used pairwise to specify which edge(s) are of interest. TCTL3 specifies edges for channels 7 through 4 and TCTL4 specifies edges for channels 3 through 0.