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Address decoding using logic gates
Continuing from the previous example, the EEPROM chip is enabled only when the left most 6 bits in the address equal 001000. The decoding circuit for the EEPROM can be a six-input NAND gate. If you cannot find a six-input NAND gate, you can build it by using smaller gates. E.g., you can use three AND gates and inverters to build the address decoding circuit.
Using the same method, we can also make digital circuits that enable the RAM chip and the ROM chip.
Using logic gates to build address decoding circuits is very useful for understanding the concept; however, it is sometimes cumbersome in practice. Other techniques for implementing address decoding circuits are explained next.
Exercise 9.3: Draw address decoding circuits for RAM and ROM specified in the memory map.