First page Back Continue Last page Overview Graphics
Partial address decoding
- CPU supports large address space and
- memory used by system is small.
Technique: Decode only some of the address lines.
Limitation: Program must not address the memory spaces that are not decoded.
Example: 2K of memory in 1M of addressable space.
- Leftmost 9 address bits are always zero.
- If program never refers to addresses above 2K-1, don't need to decode leftmost 9 address bits.
- (What happens if it does refer to an address above 2K-1?)
Although the CPU can address a large memory space, a simple system may only use a small part of that available memory space. When a small memory chip is used with a large microprocessor, an address decoding circuit may need several chips. It is desirable to use a lower chip count to reduce the system cost. Partial address decoding techniques can be used is some cases to achieve this goal.
For example, if the CPU of a system can address 1M memory and the actual memory in the system is only 2K, the leftmost 9 address bits are always 0 for all the available memory addresses. If one can make sure that the program never refers to address above 2K-1 program, the leftmost 9 bits do not need to be used in address decoding.
If the leftmost 9 bits are not used in the decoding circuit and the program does read an address x above 2K-1, the memory address y = x - n2K will be read, where n = the largest integer to make 0 y < 2K. For example, if x = 4000, y = 0 (n =2).