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Register Block (configured using INITRG) has default address 0x0000.
RAM has default address 0x0800 (changed using INITRM).
EEPROM has default address 0x0D00 (changed using INITEE).
FLASH EEPROM; 0x8000; MISC bits 0 and 1.
Possible start addresses affected by number of bits available for indicating start address.
- 5 bits for register block and RAM
- 4 for EEPROM
- 1 for FLASH EEPROM.
In this lecture, we review the concepts and use of the M68HC12B Standard Timer Module (TIM). The primary references for this material are the M68HC12B Family Data Sheet and sections 7.5 through 7.8 (pp. 244-278) of the textbook by Pack and Barrett.
The heart of the timer module is the 16-bit free-running counter. The input and output capture functions capture the value of the couter at the occurrence of an input or output event. Events to be captured are specified using control registers.
After discussing the timer module, we'll go on to discuss mapping of internal (on-chip) resources. Addresses of RAM, EEPROM, and the register block can be changed from the defaults by writing to the appropriate initialization registers.