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This circuit shows the conceptual circuit of an output port. Here we assume that the output port has 8 bits. The latch includes 8 parallel D flip flops. The function of the D flip flops is to separate the port from the data bus. The latch is triggered by an address decoding circuit. The method for designing the address decoding circuit for I/O is the same as for a memory component. The address decoding circuit is designed in such a way that the flip flops are clocked only when the particular I/O address is on the address bus.

Some microprocessors provide an iow signal directly. For example, the 68HC12’s r/w control signal can be used as an iow. Other microprocessors do not provide an iow control signal directly. For example, the Intel 8086 processor provides two signals: “write” and “M/IO”. These two signals need to be combined to generate the iow control signal.