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ATD Control Register ATDCTL4
ATDCTL4 is used to control sample timing.
ATD time base is the P clock.
Total conversion time consists of
- Fixed initial sample time is 2 ATD clock cycles.
- Fixed transfer time is 4 ATD clock cycles.
- Fixed resolution time of 10 ATD clock cycles.
- Programmable “final sample time” of 2, 4, 8, or 16 clock cycles
The ATD clock cycle can be chosen using prescalar bits to divide the P clock frequency.