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Conceptual input port circuit
This circuit shows the concept of an input port circuit. Here we assume that the input port has n bits, where n usually equals to 8 or 16. The buffer includes n parallel tri-state buffer circuits. The function of the tri-state buffer is to separate the port from the data bus. The buffer is enabled by an address decoding circuit. The method for designing the address decoding circuit for I/O is the same as that for memory components. The address decoding circuit should be designed in such a way that the port can be read only when the correct I/O address is on the address bus. One may think of the I/O port as a one-address memory chip.
Some microprocessors provide an ioread signal directly. For example the 68HC12’s r/w control signal can be used as an ioread. Other microprocessors do not provide an ioread control signal directly. An example is the Intel 8086 processor which provides two signals: “read” and “M/IO”. The designer then needs to combine these two signals to generate an ioread control signal.