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I2C byte transfer and acknowledge


Notes:

The I2C (Inter Integrated Circuit) bus, developed by Philips Semiconductors, provides a three-wire bi-directional interface between multiple devices. I2C uses two lines, one for synchronization clock (SCL) and one for data and acknowledgement (SDA). The BUS MASTER is the chip issuing the commands on the BUS. The IC that initiates a data transfer on the bus is considered the BUS MASTER and all the others are regarded as the bus slaves. The IC bus is a Multi-MASTER BUS. More than one IC capable of initiating data transfer can be connected to it. I2C bus transfers consist of a number of bytes framed by a start condition and a stop condition. When bus transfers are not taking place, both SDA and SCL float high. The transmitter indicates the start condition by generating a falling edge of SDA followed by the falling edge of SCL within the same clock cycle. The end of a data transfer generates a rising edge of SCL followed by the rising edge of SDA within the same clock cycle. The receivers keep monitoring these two lines. Once the transfer starts, eight data bits are sent according to the clock cycles. In the ninth clock cycle, the receiver indicates the success of data transfer by raising SDA high; otherwise, SDA is low. Multiple bytes can be sent by repeating this 9-clock cycle. The transmitter indicates the end of transmission by generating the rising edge of SCL followed by the rising edge of SDA within the same clock cycle. The first byte on SDA after the start is the control byte. The left seven bits of a control byte indicate the destination address (devices). The rightmost bits of the control byte indicates the data transfer is write (sent) or read (receive).