First page Back Continue Last page Overview Graphics
I2C bus: protocol
When bus transfers are not taking place, both SDA and SCL float high.
- start condition by generating a falling edge on SDA followed by a falling edge on SCL within the same clock cycle;
- end of a data transfer by generating a rising edge on SCL followed by a rising edge on SDA within the same clock cycle.
Receivers monitor SDA and SCL.
Once the transfer is initiated, eight data bits are sent.
In the ninth clock cycle, the receiver indicates the success of the data transfer by raising SDA high; otherwise, SDA is low.
Multiple bytes can be sent by repeating this 9-clock cycle.