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J1850 - single wire with variable pulse width
1 (7 volts) = long (128 s) low or short (64 s) high
0 (0 volts) = short (64 s) low or long (128 s) high
Start frame = 200 s high after transition for low to high
End of frame = 280 s low after transition for high to low
Use cyclic redundancy check (CRC)
- appended as the last byte of message
- error-free CRC is $C4
Variable pulse width modulation is an encoding technique. It uses 0 volts and 7 volts to represent logic levels 0 and 1, respectively. When no one is sending data to the bus the bus stays low. When a device wants to send data, the device pulls the data line high for 200 s. When a device wants to end data transfer, the device pulls the data line low for at least 280 s. The time for data transfer is divided into multiple units of 64 s. A 1 in the data stream is represented by either a short high ( 1 volt for 64 s) or a long low (0 volt for 128 s). A 0 in the data stream is represented by either a short low (0 volt for 64 s) or a long high (7 volt for 128 s).
The last byte in a frame transfer is the Cyclic Redundancy Check (CRC). The error free CRC should always be $C4. Any number other than $C4 means an error occurred in data transfer.