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J1850 - dual wire with pulse width modulation
1 (7 volts) ↔ 67% duty cycle
0 (0 volts) ↔ 33% duty cycle
End of frame
Pulse width modulation is another encoding technique. It uses 0 volts and 7 volts to represent logic levels 0 and 1, respectively. When no one is sending data to the bus the bus stays low. When a device wants to send data, the device pulls the data line high for 50 s. When a device wants to end data transfer, the device pulls the data line low for at least 70 s. The time for data transfer is divided into units of 24 s. A 1 in the data is represented by a 67% duty cycle signal and a 0 in the data is represented by a 33% duty cycle signal.
The last byte in a frame transfer is the Cyclic Redundancy Check (CRC). The error free CRC should always be $C4. Any number other than $C4 means an error occurred in data transfer.