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- Configurable for 8 or 9 data bits.
- One of the data bits may be designated as a parity bit.
- If selected, parity is generated in hardware.
- Receiver parity errors are flagged in hardware.
- Receiver wakeup
- Idle line detect
- Loop-back mode
Port pins TxD (PS1) and RxD (PS0) provide external interface.
When copying a set of data from one memory (or I/O) location to another memory (or I/O) location, the microprocessor needs to read the data from the source location into the CPU and then write the data to the destination location. Since executing each read or write instruction may take several clock cycles, the data transfer is slow.
A DMA chip is a special processor that just does read and write operations. Each read or write takes only one clock cycle.
There are some clock cycles that the CPU does not need the buses. DMA can use these bus cycles to transfer data.