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When microprocessors can do fast calculation, the speed of information transfer between CPU and memory may become a bottleneck. There are several factors that affect the data transfer rate
the speed of the buses,
the width of the data bus, and
the speed of the memory chips.
If the speed of the bus is limited by the length and physical layout of the bus, more buses working in parallel can be one solution to the problem. (The Harvard architecture does this, using two address buses and two data buses.) If the speed of the buses is limited by the access speed of the memory chips, cache memory can be a solution to the problem. Another approach is to use wider data buses to reduce the number of data transfers.