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RISC stands for Reduced Instruction Set Computer.
CISC stands for Complete Instruction Set Computer.
The addressing modes of RISC are simpler than CISC.
One RISC instruction usually does less work than one CISC instruction.
RISC processors are well suited to take advantage of pipelined architectures (because instructions are simple and most take the same amount of time to execute).
In previous lectures, we learned a subset of the instruction set of the 68HC12 microcontroller, just large enough to cover the basic programming needs for the laboratory experiments. However, we saw that programs could be shortened considerably by using the most specific instructions possible, e.g. the brset and brclr instructions. A computer that tries to minimize the number of lines of code required to write a program is called a complete-instruction-set-computer (CISC). This makes it easier to write programs at assembly level.
However, when the instruction sets and addressing modes become complex, it is difficult to write a good high-level language compiler that can select the best assembly instruction. Moreover, complex instructions and addressing modes make it harder to use the pipeline architecture efficiently. Therefore, a very different approach, reduced-instruction-set-computer (RISC) has become popular. RISC processors are designed with compiler efficiency in mind. Only instructions that can be used by the compiler are included in the instruction set. For example, complex addressing modes are usually not included in RISC processors.